LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 41

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4 PCI Cache Mode
2.4.1 Load and Store Instructions
2.4.2 3.3 V/5 V PCI Interface
2.4.3 Additional Access to General Purpose Pins
The LSI53C825A supports the PCI specification for an 8-bit
Size
register provides the ability to sense and react to nonaligned addresses
corresponding to cache line boundaries. In conjunction with the
Line Size
Write and Invalidate are each software enabled or disabled to allow the
user full flexibility in using these commands. For more information on PCI
cache mode operations, refer to
The LSI53C825A supports the Load and Store instruction type, which
simplifies the movement of data between memory and the internal chip
registers. It also enables the LSI53C825A to transfer bytes to addresses
relative to the
information on the Load and Store instructions, refer to
SCRIPTS Instruction Set.”
The LSI53C825A can attach directly to a 3.3 V or a 5 V PCI interface,
due to separate V
to be used on the universal board recommended by the PCI Special
Interest Group.
The LSI53C825A can access the GPIO0 and GPIO1 general purpose
pins through register bits in the PCI configuration space, instead of using
the
register space to control these pins. In the LSI Logic SDMS software, the
configuration bits control pins as the clock and data lines, respectively.
To access the GPIO[1:0] pins through the configuration space, connect
a 4.7 k
internal pull-up that is sensed shortly after chip reset. If the pin is sensed
high, GPIO[1:0] access is disabled; if it is low, GPIO[1:0] access is
enabled. Additionally, if GPIO[1:0] access has been enabled through the
PCI Cache Mode
General Purpose Pin Control (GPCNTL)
register located in PCI configuration space. The
resistor between the MAD7 pin and V
register, the PCI commands Read Line, Read Multiple, and
Data Structure Address (DSA)
DD
pins for the PCI bus drivers. This allows the devices
Chapter 3, “Signal Descriptions.”
register in the operating
register. For more
SS
. MAD7 contains an
Cache Line Size
Chapter 5, “SCSI
Cache Line
Cache
2-17