LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 149

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Register: 0x23 (0xA3)
Chip Test Six (CTEST6)
Read/Write
DF
Operating Registers
7
0
0
DMA FIFO
Writing to this register writes data to the appropriate byte
lane of the DMA FIFO as determined by the FBL bits in
the
register unloads data from the appropriate byte lane of
the DMA FIFO as determined by the FBL bits in the
Test Four (CTEST4)
loaded into the top of the FIFO. Data read out of the FIFO
is taken from the bottom. To prevent DMA data from
being corrupted, this register should not be accessed
before starting or restarting SCRIPTS operation. Write to
this register only when testing the DMA FIFO using the
Chip Test Four (CTEST4)
while the test mode is not enabled produces unexpected
results.
Chip Test Four (CTEST4)
0
0
DF
register. Data written to the FIFO is
0
register. Writing to this register
register. Reading this
0
0
Chip
0
0
[7:0]
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