LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 34

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.1.3.8 Read Multiple with Read Line Enabled
2.1.3.9 Unsupported PCI Commands
2.2 SCSI Functional Description
2.2.1 SCSI Core
2-10
When both the Read Multiple and Read Line modes are enabled, the
Read Line command is not issued if the above conditions are met.
Instead, a Read Multiple command is issued, even though the conditions
for Read Line are met.
If the Read Multiple mode is enabled and the Read Line mode is
disabled, Read Multiple commands are issued if the Read Multiple
conditions are met.
The LSI53C825A does not respond to reserved commands, special
cycle, dual address cycle, or interrupt acknowledge commands as a
slave. It never generates these commands as a master.
The LSI53C825A is composed of three functional blocks: the
the
supported by the SDMS, a complete software package that supports the
LSI Logic product line of SCSI processors and controllers. The PCI Bus
Power Management
this chapter.
The SCSI core supports the 8-bit or 16-bit data bus. It supports SCSI
synchronous transfer rates up to 20 Mbytes/s, and asynchronous transfer
rates up to 10 Mbytes/s on a 16-bit wide SCSI bus. The SCSI core can
be programmed with SCSI SCRIPTS, making it easy to “fine tune” the
system for specific mass storage devices or SCSI-3 requirements.
The SCSI core offers low level register access or a high level control
interface. Like first generation SCSI devices, the LSI53C825A SCSI core
can be accessed as a register oriented device. The ability to sample
and/or assert any signal on the SCSI bus can be used in error recovery
and diagnostic procedures. In support of loopback diagnostics, the SCSI
core may perform a self-selection and operate as both an initiator and a
target.
Functional Description
DMA
Core, and the
support (LSI53C825AE) is discussed at the end of
SCRIPTS
Processor. The LSI53C825A is fully
SCSI
Core,