LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 12

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LSI53C825AJ

Manufacturer Part Number
LSI53C825AJ
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53C825AJ

Lead Free Status / RoHS Status
Not Compliant
Tables
xii
B.2
B.3
B.4
2.1
2.2
2.3
2.4
2.5
2.6
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
5.1
5.2
Contents
64 Kbyte Interface with 150 ns Memory
256 Kbyte Interface with 150 ns Memory
512 Kbyte Interface with 150 ns Memory
PCI Bus Commands and Encoding Types
External Memory Support
Bits Used for Parity Control and Generation
SCSI Parity Control
SCSI Parity Errors and Interrupts
Differential Mode
LSI53C825A, LSI53C825AJ, LSI53C825AE, and
LSI53C825AJE Power and Ground Pins
System Signals
Address and Data Signals
Interface Control Signals
Arbitration Signals
Error Reporting Signals
SCSI Bus Interface Signals
Additional Interface Signals
External Memory Interface Signals
JTAG Signals (LSI53C825AJ, LSI53C825AJE Only)
Subsystem Data Configuration Table for the
LSI53C825AE (PCI Rev ID 0x26)
Subsystem Data Configuration Table for the
LSI53C825A (PCI Rev ID 0x14) Revision G Only
External Memory Support
PCI Configuration Register Map
LSI53C825A Register Map
Synchronous Clock Conversion Factor
Examples of Synchronous Transfer Periods and
Rates for SCSI-1
Example Transfer Periods and Rates for Fast SCSI-2
Maximum Synchronous Offset
Timeout Periods
Timeout Periods, 50 MHz Clock
SCRIPTS Instructions
Read/Write Instructions
2-16
2-21
2-22
2-23
2-28
3-10
3-11
3-14
3-15
3-16
3-16
3-17
4-19
4-29
4-33
4-33
4-34
4-82
4-83
5-27
B-2
B-3
B-4
2-3
3-4
3-6
3-7
3-8
3-9
3-9
4-2
5-3

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