LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 57

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.10 Select/Reselect During Selection/Reselection
2.4.11 Synchronous Operation
2.4.11.1 Determining the Data Transfer Rate
In multithreaded SCSI I/O environments, it is not uncommon to be
selected or reselected while trying to perform selection/reselection. This
situation may occur when a SCSI controller (operating in initiator mode)
tries to select a target and is reselected by another. The Select SCRIPTS
instruction has an alternate address to which the SCRIPTS jumps when
this situation occurs. The analogous situation for target devices is being
selected while trying to perform a reselection.
Once a change in operating mode occurs, the initiator SCRIPTS should
start with a Set Initiator instruction or the target SCRIPTS should start
with a Set Target instruction. The Selection and Reselection Enable bits
(SCID bits 5 and 6, respectively) should both be asserted so that the
LSI53C825A may respond as an initiator or as a target. If only selection
is enabled, the LSI53C825A cannot be reselected as an initiator. There
are also status and interrupt bits in the
(SIST0)
indicating that the LSI53C825A has been selected (bit 5) and reselected
(bit 4).
The LSI53C825A can transfer synchronous SCSI data in both initiator
and target modes. The
synchronous offset and the transfer period. It may be loaded by the CPU
before SCRIPTS execution begins, from within SCRIPTS using a Table
Indirect I/O instruction, or with a Read-Modify-Write instruction.
The LSI53C825A can receive data from the SCSI bus at a synchronous
transfer period as short as 80 or 160 ns (with a 50 MHz clock),
regardless of the transfer period used to send data. The LSI53C825A
can receive data at one-fourth of the divided SCLK frequency. Depending
on the SCLK frequency, the negotiated transfer period, and the
synchronous clock divider, the LSI53C825A can send synchronous data
at intervals as short as 100 ns for fast SCSI and 200 ns for SCSI-1.
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C825A. A brief description of the bits is provided
below.
PCI Cache Mode
and
SCSI Interrupt Enable Zero (SIEN0)
SCSI Transfer (SXFER)
SCSI Interrupt Status Zero
register controls both the
registers, respectively,
2-33