LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 43

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.5 Big and Little Endian Support
Because of package limitations, the LSI53C825AJ replaces the TESTIN,
MAC/_TESTOUT, BIG_LIT, and SDIRP1 signals with the JTAG boundary
scan signals.
The LSI53C825A supports both big and little endian byte ordering
through pin selection. The LSI53C825AJ operates in little endian mode
only (the BIG_LIT pin is replaced by one of the JTAG boundary scan
signals). In big endian mode, the first byte of an aligned SCSI to PCI
transfer is routed to lane three and succeeding transfers are routed to
descending lanes. This mode of operation also applies to data transfers
over the add-in ROM interface. The byte of data accessed at location
0x0000 from memory is routed to lane three, and the data at location
0x0003 is routed to byte lane 0. In little endian mode, the first byte of an
aligned SCSI to PCI transfer is routed to lane zero and succeeding
transfers are routed to ascending lanes. This mode of operation also
applies to the add-in ROM interface. The byte of data accessed at
location 0x0000 from memory is routed to lane zero, and the data at
location 0x0003 is routed to byte lane 3.
The Big_Lit pin gives the LSI53C825A the flexibility of operating with
either big or little endian byte orientation. Internally, in either mode, the
actual byte lanes of the DMA FIFO and registers are not modified. The
LSI53C825A supports slave accesses in big or little endian mode.
When a Dword is accessed, no repositioning of the individual bytes is
necessary since Dwords are addressed by the address of the least
significant byte. SCRIPTS always uses Dwords in 32-bit systems, so
compatibility is maintained between systems using different byte
orientations. When less than a Dword is accessed, individual bytes must
be repositioned. Internally, the LSI53C825A adjusts the byte control logic
of the DMA FIFO and register decodes to access the appropriate byte
lanes. The registers always appear on the same byte lane, but the
address of the register are repositioned.
PCI Cache Mode
When RST/ is asserted during boundary scan testing, the expected
output on the SCSI pins must be HIGH-Z condition, and not what is
contained in the boundary scan data registers for the SCSI pin
output cells.
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