LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 221

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5.7.1 First Dword
Allowing the LSI53C825A to perform memory moves frees the system
processor for other tasks and moves data at higher speeds than available
from current DMA controllers. Up to 16 Mbytes may be transferred with
one instruction. There are two restrictions:
The
(DSA)
Move. However, the contents of the
register are preserved.
IT[2:0]
R
NF
Memory Move Instructions
Both the source and destination addresses must start with the same
address alignment A[1:0]. If the source and destination are not
aligned, then an illegal instruction interrupt occurs. For the PCI
Cache Line Size
destination must be the same distance from a cache line boundary.
Indirect addresses are not allowed. A burst of data is fetched from
the source address, put into the DMA FIFO and then written out to
the destination address. The move continues until the byte count
decrements to zero, then another SCRIPTS is fetched from system
memory.
DMA SCRIPTS Pointer Save (DSPS)
Note:
registers are additional holding registers used during the Memory
This bit has no effect unless the Prefetch Enable bit in the
DMA Control (DCNTL)
SCRIPTS instruction prefetching, see
Instruction Type - Memory Move
The IT bit configuration (110) defines a Memory Move
Instruction Type.
Reserved
These bits are reserved and must be zero. If any of these
bits are set, an illegal instruction interrupt occurs.
No Flush
When this bit is set, the LSI53C825A performs a Memory
Move without flushing the prefetch unit. When this bit is
cleared, the Memory Move instruction automatically
flushes the prefetch unit. Use the No Flush option if the
source and destination are not within four instructions of
the current Memory Move instruction.
register setting to take effect, the source and
Data Structure Address (DSA)
register is set. For information on
and
Data Structure Address
Chapter
2.
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