LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 207

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

5.4.2 Second Dword
R
ACK
R
ATN
R
SA
I/O Instruction
Reserved
Set/Clear SACK/
Reserved
Set/Clear SATN/
These two bits are used in conjunction with a Set or Clear
instruction to assert or deassert the corresponding SCSI
control signal. Bit 6 controls the SCSI SACK/ signal. Bit 3
controls the SCSI SATN/ signal.
The Set instruction is used to assert SACK/ and/or SATN/
on the SCSI bus. The Clear instruction is used to
deassert SACK/ and/or SATN/ on the SCSI bus. The
corresponding bit in the
(SOCL)
instruction used.
Since SACK/ and SATN/ are Initiator signals, they are not
asserted on the SCSI bus unless the LSI53C825A is
operating as an Initiator or the SCSI Loopback Enable bit
is set in the
The Set/Clear SCSI ACK/, ATN/ instruction is used after
message phase Block Move operations to give the
Initiator the opportunity to assert attention before
acknowledging the last message byte. For example, if the
Initiator wishes to reject a message, it issues an Assert
SCSI ATN instruction before a Clear SCSI ACK
instruction.
Reserved
Start Address
This 32-bit field contains the memory address to fetch the
next instruction if the selection or reselection fails.
If relative or table relative addressing is used, this value
is a 24-bit signed offset relative to the current
SCRIPTS Pointer (DSP)
register is set or cleared depending on the
SCSI Test Two (STEST2)
SCSI Output Control Latch
register value.
register.
DMA
[31:0]
[8:7]
[5:4]
[2:0]
5-23
6
3