LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 203

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

RA
I/O Instruction
1. If the LSI53C825A is selected before being
2. If the LSI53C825A is reselected, it fetches the next
3. If the CPU sets the SIGP bit in the Interrupt Status
minimum of one Bus Free delay (400 ns), after the
LSI53C825A receives a Disconnect Message or a
Command Complete Message.
Wait Reselect Instruction
Set Instruction
When the SACK/ or SATN/ bits are set, the
corresponding bits in the
(SOCL)
corresponding bit in the
register is also set. When the carry bit is set, the
corresponding bit in the ALU is set.
Clear Instruction
When the SACK/ or SATN/ bits are cleared, the
corresponding bits are cleared in the
SCSI Output Control Latch (SOCL)
target bit is cleared, the corresponding bit in the
Control Zero (SCNTL0)
carry bit is cleared, the corresponding bit in the ALU is
cleared.
Relative Addressing Mode
When this bit is set, the 24-bit signed value in the
Next Address (DNAD)
displacement from the current
(DSP)
reselected, it fetches the next instruction from the
address pointed to by the 32-bit jump address field
stored in the
Manually set the LSI53C825A to Target mode when it
is selected.
instruction from the address pointed to by the
SCRIPTS Pointer (DSP)
Zero (ISTAT0) register, the LSI53C825A aborts the
Wait Reselect instruction and fetches the next
instruction from the address pointed to by the 32-bit
jump address field stored in the
(DNAD)
address. Use this bit only in conjunction with the
register are set. When the target bit is set, the
register.
DMA Next Address (DNAD)
register is used as a relative
register is cleared. When the
SCSI Control Zero (SCNTL0)
SCSI Output Control Latch
register.
DMA SCRIPTS Pointer
DMA Next Address
register. When the
register.
SCSI
DMA
DMA
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