LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 26

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.1.2 PCI Bus Commands and Functions Supported
2-2
The lower 128 bytes of the LSI53C825A configuration space hold system
parameters while the upper 128 bytes map into the LSI53C825A
operating registers. For all PCI cycles except configuration cycles, the
LSI53C825A registers are located on the 256-byte block boundary
defined by the base address assigned through the configured register.
The LSI53C825A operating registers are available in both the upper and
lower 128-byte portions of the 256-byte space selected.
At initialization time, each PCI device is assigned a base address (in the
case of the LSI53C825A, the upper 24 bits of the address are selected)
for memory accesses and I/O accesses. On every access, the
LSI53C825A compares its assigned base addresses with the value on
the Address/Data bus during the PCI address phase. If the upper 24 bits
match, the access is for the LSI53C825A and the low-order eight bits
define the register to be accessed. A decode of C_BE/ [3:0] determines
which registers and what type of access is to be performed.
I/O Space – PCI defines memory space as a contiguous 32-bit memory
address that is shared by all system resources, including the
LSI53C825A.
memory area this device will occupy.
Memory Space – PCI defines I/O space as a contiguous 32-bit I/O
address that is shared by all system resources, including the
LSI53C825A.
area this device will occupy.
Bus commands indicate to the target the type of transaction the master
is requesting. Bus commands are encoded on the C_BE/[3:0] lines
during the address phase. PCI bus command encoding and types appear
in
Functional Description
Table
2.1.
Base Address One (Memory)
Base Address Zero (I/O)
determines which 256-byte I/O
determines which 256-byte