LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 67

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.4.14.3 SWIDE Register
2.4.14.4 SODL Register
2.4.14.5 Chained Block Move SCRIPTS Instruction
cleared by the microprocessor or through SCRIPTS. The bit can also be
used by the microprocessor or SCRIPTS for error detection and recovery
purposes.
This register stores data for partial byte data transfers. For receive data,
the
partial SCSI transfer which has not yet been transferred to memory. This
stored data may be a residue byte (and therefore ignored) or it may be
valid data that is transferred to memory at the beginning of the next Block
Move instruction.
For send data, the low-order byte of the
register holds the low-order byte of a partial memory transfer which has
not yet been transferred across the SCSI bus. This stored data is usually
“married” with the first byte of the next data send transfer, and both bytes
are sent across the SCSI bus at the start of the next data send block
move command.
A chained Block Move SCRIPTS instruction is primarily used to transfer
consecutive data send or data receive blocks. Using the chained Block
Move instruction facilitates partial receive transfers and allows correct
partial send behavior without additional opcode overhead. Behavior of
the chained Block Move instruction varies slightly for sending and
receiving data.
For receive data (Data-In for initiator or Data-Out for target), a chained
Block Move instruction indicates that if a partial transfer occurred at the
end of the instruction, the WSR flag is set. The high-order byte of the
last SCSI transfer is stored in the
rather than transferred to memory. The contents of the
Residue (SWIDE)
at the start of the chained block move data stream. Since the byte count
always represents data transfers to/from memory (as opposed to the
SCSI bus), the byte transferred out of the
register is one of the bytes in the byte count. If the WSR bit is cleared
when a receive data chained Block Move instruction is executed, the data
PCI Cache Mode
SCSI Wide Residue (SWIDE)
register should be the first byte transferred to memory
register holds the high-order byte of a
SCSI Wide Residue (SWIDE)
SCSI Output Data Latch (SODL)
SCSI Wide Residue (SWIDE)
SCSI Wide
register
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