LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 36

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.2.5 SDMS: The Total SCSI Solution
2-12
instructions or Table Indirect information from the internal RAM, these
fetches remain internal to the chip and do not use the PCI bus. Other
types of access to the RAM by the LSI53C825A use the PCI bus, as if
they were external accesses. The MAD5 pin enables the 4 K internal
RAM. To disable the internal RAM, connect a 4.7 k
the MAD5 pin and V
The RAM can be relocated by the PCI system BIOS anywhere in 32-bit
address space. The RAM Base Address register in PCI configuration
space contains the base address of the internal RAM. This register is
similar to the ROM Base Address register in PCI configuration space. To
simplify loading of SCRIPTS instructions, the base address of the RAM
will appear in the
the
from the PCI bus and is visible to any bus mastering device on the bus.
External accesses to the RAM (i.e., by the CPU) follow the same timing
sequence as a standard slave register access, except that the target wait
states required drop from 5 to 3.
A complete set of development tools is available for writing custom
drivers with SCSI SCRIPTS. For more information on the SCSI SCRIPTS
instructions supported by the LSI53C825A, see
SCRIPTS Instruction Set.”
For users who do not need to develop custom drivers, LSI Logic provides
a total SCSI solution in PC environments with the SDMS. SDMS software
provides BIOS driver support for hard disk, tape, and removable media
peripherals for the major PC-based operating systems.
SDMS software includes a SCSI BIOS to manage all SCSI functions
related to the device. It also provides a series of SCSI device drivers that
support most major operating systems. SDMS software supports a
multithreaded I/O application programming interface (API) for user
developed SCSI applications. SDMS software supports both the ASPI
and CAM SCSI software specifications.
Functional Description
Chip Test Two (CTEST2)
Scratch Register B (SCRATCHB)
SS
.
register is set. The RAM is byte accessible
Chapter 5, “SCSI
register when bit 3 of
resistor between