LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 37

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

2.2.6 Prefetching SCRIPTS Instructions
When enabled (by setting the Prefetch Enable bit in the
(DCNTL)
8 Dwords of instructions. The prefetch logic automatically determines the
maximum burst size that it can perform, based on the burst length as
determined by the values in the
cannot perform bursts of at least 4 Dwords, it disables itself. While the
LSI53C825A is prefetching SCRIPTS instructions, the PCI
Size
Multiple, and Write and Invalidate commands are not used.
The LSI53C825A may flush the contents of the prefetch unit under
certain conditions, listed below, to ensure that the chip always operates
from the most current version of the software. When one of these
conditions apply, the contents of the prefetch unit are flushed
automatically.
SCSI Functional Description
On every Memory Move instruction. The Memory Move instruction is
often used to place modified code directly into memory. To make
sure that the chip executes all recent modifications, the prefetch unit
flushes its contents and loads the modified code every time an
instruction is issued. To avoid inadvertently flushing the prefetch unit
contents, use the No Flush option for all Memory Move operations
that do not modify code within the next 8 Dwords. For more
information on this instruction, refer to
Instructions,”
On every Store instruction. The Store instruction may also be used
to place modified code directly into memory. To avoid inadvertently
flushing the prefetch unit contents, use the No Flush option for all
Store operations that do not modify code within the next 8 Dwords.
On every write to the DSP.
On all Transfer Control instructions when the transfer conditions are
met. This is necessary because the next instruction to be executed
is not the sequential next instruction in the prefetch unit.
When the Prefetch Flush bit
unit flushes whenever this bit is set. The bit is self-clearing.
register value does not have any effect and the Read Line, Read
register), the prefetch logic in the LSI53C825A fetches
in
Chapter 5, “SCSI SCRIPTS Instruction Set.”
DMA Mode (DMODE)
(DMA Control
Section 5.7, “Memory Move
(DCNTL), bit 6) is set. The
register. If the unit
DMA Control
Cache Line
2-13