LSI53C825AJ LSI, LSI53C825AJ Datasheet - Page 195

• Manufacturer Part Number: LSI53C825AJ
• Manufacturer: LSI

Specifications of LSI53C825AJ

• Lead Free Status / RoHS Status: Not Compliant

Block Move Instructions
1. The LSI53C825A verifies that it is connected to the
2. The LSI53C825A waits for an unserviced phase to
3. The LSI53C825A compares the SCSI phase bits in
4. If the SCSI phase bits match the value stored in the
Initiator Mode
In Target mode, the Opcode bit defines the following
operations:
OPC
0
1
These instructions perform the following steps:
SCSI bus as an Initiator before executing this
instruction.
occur. An unserviced phase is any phase (with SREQ/
asserted) for which the LSI53C825A has not yet
transferred data by responding with a SACK/.
the
SCSI phase lines stored in the
(SSTAT1)
when SREQ/ is asserted.
SCSI
LSI53C825A transfers the number of bytes specified
in the
the address pointed to by the
(DNAD)
data transfer ends on an odd byte boundary, the
LSI53C825A stores the last byte in the
Residue (SWIDE)
or in the
during a send operation. This byte is combined with
the first byte from the subsequent transfer so that a
wide transfer can complete.
DMA Command (DCMD)
Instruction Defined
CHMOV
MOVE
SCSI Status One (SSTAT1)
DMA Byte Counter (DBC)
register. If the opcode bit is cleared and a
SCSI Output Control Latch (SOCL)
register. These phase lines are latched
register during a receive operation,
register with the latched
DMA Next Address
SCSI Status One
register starting at
register, the
SCSI Wide
register
5-11