MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 635
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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23.15 OnCE, JTAG, and Boundary Scan Timing
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
No.
1. Parameters 9 and 10 apply to the DE pin when used to enable OnCE. Parameters 15 and 16 apply to the DE pin when used
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
to request the processor to enter debug mode.
TCLK frequency of operation
TCLK cycle period
TCLK clock pulse width
TCLK rise and fall times
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low-to-boundary scan output data valid
TCLK low-to-boundary scan output high Z
TMS, TDI, and DE input data setup time to TCLK rise
TMS, TDI, and DE input data hold time after TCLK rise
TCLK low to TDO data valid
TCLK low to TDO high Z
TRST assert time
TRST setup time (negation) to TCLK high
DE input data setup time to CLKOUT rise
DE input data hold time after CLKOUT rise
CLKOUT high to DE data valid
CLKOUT high to DE high Z
TCLK INPUT
Table 23-15. OnCE, JTAG, and Boundary Scan Timing
Characteristics
(V
Freescale Semiconductor, Inc.
DD
Figure 23-8. Test Clock Input Timing
For More Information On This Product,
4
= 2.7 to 3.6 V, V
V
Preliminary Electrical Specifications
IH
Go to: www.freescale.com
V
IL
(1)
(1)
3
SS
= 0 V, T
(1)
4
(1)
2
Symbol
t
t
t
t
A
t
t
t
t
t
t
TAPDST
TAPDHT
TRSTST
TRSTAT
TDODV
t
f
t
BSDST
BSDHT
t
t
TDODZ
DEDST
DEDHT
t
t
t
BSDV
DEDV
DEDZ
JCYC
JCYC
BSDZ
JCRF
JCW
= T
OnCE, JTAG, and Boundary Scan Timing
L
to T
Preliminary Electrical Specifications
3
H
Min
100
25
24
15
10
10
dc
)
2
0
5
0
0
7
0
0
2
0
0
1/2 x f
Advance Information
Max
40
40
25
20
10
—
—
—
—
—
—
—
—
—
—
3
9
sys
MHz
Unit
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
635
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