MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 287

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13.3.2 Stop Mode
13.4 Interrupt/General-Purpose I/O Pin Descriptions
13.5 Memory Map and Registers
13.5.1 Memory Map
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
0x00c6_0000
0x00c6_0002
0x00c6_0004
0x00c6_0006
1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
2. Writing to reserved address locations has no effect, and reading returns 0s.
Address
only addresses have no effect and result in a cycle termination transfer error.
NOTE:
EPORT Data Direction Register (EPDDR)
EPORT Data Register (EPDR)
EPORT Flag Register (EPFR)
In stop mode, there are no clocks available to perform the edge-detect
function. Only the level-detect logic is active (if configured) to allow any
low level on the external interrupt pin to generate an interrupt (if enabled)
to exit stop mode.
The input pin synchronizer is bypassed for the level-detect logic since no
clocks are available.
All pins default to general-purpose input pins at reset. The pin value is
synchronized to the rising edge of CLKOUT when read from the EPORT
Pin Data Register (EPPDR). The values used in the edge/level detect
logic are also synchronized to the rising edge of CLKOUT. These pins
use Schmitt triggered input buffers which have built in hysteresis
designed to decrease the probability of generating false edge-triggered
interrupts for slow rising and falling input signals.
This subsection describes the memory map and register structure.
Refer to
EPORT has a base address of 0x00c6_0000.
Table 13-1. Edge Port Module Memory Map
Freescale Semiconductor, Inc.
Bits 15–8
For More Information On This Product,
Table 13-1
EPORT Pin Assignment Register (EPPAR)
Edge Port Module (EPORT)
Go to: www.freescale.com
for a description of the EPORT memory map. The
EPORT Interrupt Enable Register (EPIER)
EPORT Pin Data Register (EPPDR)
Interrupt/General-Purpose I/O Pin Descriptions
Reserved
Bits 7–0
(2)
Edge Port Module (EPORT)
Advance Information
Access
S/U
S/U
S
S
(1)
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