MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 495
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
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Quantity:
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19.10.6.1 Software-Initiated Single-Scan Mode
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Only the QADC can clear the single-scan enable bit. The completion
flag, completion interrupt, or queue status is used to determine when the
queue has completed.
After the single-scan enable bit is set, a trigger event causes the QADC
to begin execution with the first CCW in the queue. The single-scan
enable bit remains set until the queue is completed. After the queue
reaches completion, the QADC resets the single-scan enable bit to 0.
Writing the single-scan enable bit to a 1 or a 0 before the queue scan is
complete has no effect; however, if the queue operating mode is
changed, the new queue operating mode and the value of the
single-scan enable bit are recognized immediately. The conversion in
progress is aborted, and the new queue operating mode takes effect.
In software-initiated single-scan mode, writing a 1 to the single-scan
enable bit causes the QADC to generate a trigger event internally, and
queue execution begins immediately. In the other single-scan queue
operating modes, once the single-scan enable bit is written, the selected
trigger event must occur before the queue can start. The single-scan
enable bit allows the entire queue to be scanned once. A trigger overrun
is captured if a trigger event occurs during queue execution in an
edge-sensitive external trigger mode or a periodic/interval timer mode.
In the interval timer single-scan mode, the next expiration of the timer is
the trigger event for the queue. After queue execution is complete, the
queue status is shown as idle. The queue can be restarted by setting the
single-scan enable bit to 1. Queue execution begins with the first CCW
in the queue.
Software can initiate the execution of a scan sequence for queue 1 or 2
by selecting software-initiated single-scan mode and writing the
single-scan enable bit in QACR1 or QACR2. A trigger event is generated
internally and the QADC immediately begins execution of the first CCW
in the queue. If a pause occurs, another trigger event is generated
internally, and then execution continues without pausing.
The QADC automatically performs the conversions in the queue until an
end-of-queue condition is encountered. The queue remains idle until the
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Advance Information
Digital Control
495
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