MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 573
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Part Number:
MMC2114CFCAG33
Manufacturer:
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22.10 Non-Scan Chain Operation
22.11 Boundary Scan
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
These devices feature a low-power stop mode. The interaction of the
scan chain interface with low-power stop mode is:
Keeping the TAP controller in the test-logic-reset state will ensure that
the scan chain test logic is kept transparent to the system logic. It is
recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST
could be connected to ground. However, since there is a pullup on
TRST, some amount of current will result. JTAG will be initialized to the
test-logic-reset state on power-up without TRST asserted low due to the
JTAG power-on-reset internal input. The low-level TAP module in the
M•CORE also has the power-on-reset input.
The Boundary Scan Register contains 200 bits. This register can be
connected between TDI and TDO when EXTEST or
SAMPLE/PRELOAD instructions are selected. This register is used for
capturing signal pin data on the input pins, forcing fixed values on the
output signal pins, and selecting the direction and drive characteristics
(a logic value or high impedance) of the bidirectional and three-state
signal pins.
1. The TAP controller must be in the test-logic-reset state to either
2. The TCLK input is not blocked in low-power stop mode. To
3. The TMS, TDI, TRST pins include on-chip pullup resistors. In
Freescale Semiconductor, Inc.
For More Information On This Product,
enter or remain in the low-power stop mode. Leaving the
test-logic-reset state negates the ability to achieve low-power, but
does not otherwise affect device functionality.
consume minimal power, the TCLK input should be externally
connected to V
low-power stop mode, these three pins should remain either
unconnected or connected to V
consumption.
JTAG Test Access Port and OnCE
Go to: www.freescale.com
DD
.
DD
to achieve minimal power
JTAG Test Access Port and OnCE
Non-Scan Chain Operation
Advance Information
573
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