MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 489

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The previous situations cover normal overlap conditions that arise with
asynchronous trigger events on the two queues. An additional conflict to
consider is that the freeze condition can arise while the QADC is actively
executing CCWs. The conventional use for the debug mode is for
software/hardware debugging. When the CPU enters background
debug mode, peripheral modules can cease operation. When freeze is
detected, the QADC completes the conversion in progress, unlike the
abort that occurs when queue 1 suspends queue 2. After the freeze
condition is removed, the QADC continues queue execution with the
next CCW in sequence.
Trigger events that occur during freeze are not captured. When a trigger
event is pending for queue 2 before freeze begins, that trigger event is
remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as
soon as queue 1 is finished.
Situations 12 through 19
of all of the freeze situations.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
Figure 19-34. CCW Freeze Situation 12
Figure 19-35. CCW Freeze Situation 13
Q1:
Q2:
T1
T2
C1
C1
C2
(Figure 19-34
C2
FREEZE
FREEZE
Queued Analog-to-Digital Converter (QADC)
to
Figure
C3
C3
19-41) show examples
C4
C4
Advance Information
CF1
CF2
Digital Control
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