MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 259
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11.8.2 System Clocks Generation
11.8.3 PLL Lock Detection
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
In normal PLL clock mode, the default system frequency is two times the
reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in
SYNCR select the frequency multiplier.
When programming the PLL, do not exceed the maximum system clock
frequency listed in the electrical specifications. Use this procedure to
accommodate the frequency overshoot that occurs when the MFD bits
are changed:
Keep the maximum system clock frequency below the limit given in
Section 23. Preliminary Electrical
The lock detect logic monitors the reference frequency and the PLL
feedback frequency to determine when frequency lock is achieved.
Phase lock is inferred by the frequency relationship, but is not
guaranteed. The LOCK flag in SYNSR reflects the PLL lock status. A
sticky lock flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the
reference and the other is clocked by the PLL feedback. When the
reference counter has counted N cycles, its count is compared to that of
the feedback counter. If the feedback counter has also counted N cycles,
the process is repeated for N + K counts. Then, if the two counters still
match, the lock criteria is relaxed by 1/2 and the system is notified that
the PLL has achieved frequency lock.
1. Determine the appropriate value for the MFD and RFD fields in
2. Write a value of RFD (from step 1) + 1 to the RFD field of SYNCR.
3. Write the MFD value from step 1 to SYNCR.
4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock,
Freescale Semiconductor, Inc.
For More Information On This Product,
SYNCR. The amount of jitter in the system clocks can be
minimized by selecting the maximum MFD factor that can be
paired with an RFD factor to provide the required frequency.
write the RFD value from step 1 to the RFD field of SYNCR. This
changes the system clocks frequency to the required frequency.
Go to: www.freescale.com
Clock Module
Specifications.
Functional Description
Advance Information
Clock Module
259
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