MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 461

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Q2 PAUSE BIT SET
Q2 PAUSED
Q1 COMPLETE
Q1 IDLE/
Q2 TRIGGER EVENT
Q1 TRIGGER EVENT
Q2 ACTIVE
Q1 IDLE/
Q2 PAUSED
Q1 ACTIVE/
Q1 TRIGGER EVENT
Q1 COMPLETE
Q2 TRIGGER EVENT
Q1 TRIGGER EVENT
When the QADC finishes a queue scan, the CWP points to the CCW
where the end-of-queue condition was detected. Therefore, when the
end-of-queue condition is a CCW with the EOQ code (channel 63),
the CWP points to the CCW containing the EOQ.
When the last CCW in a queue is the last CCW table location
(CCW63), and it does not contain the EOQ code, the end-of-queue is
detected when the following CCW is read, so the CWP points to word
CCW0.
Freescale Semiconductor, Inc.
Figure 19-12. Queue Status Transition
DELAYED TRANSITION
Q2 COMPLETE
Q1 PAUSE BIT SET
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Q2 SUSPENDED
Q1 ACTIVE/
Q1 PAUSED/
Q2 PAUSED
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Q1 TRIGGER EVENT
(TEMPORARY)
Q2 TRIGGER
PENDING
Q1 IDLE/
Q1 IDLE/
Q2 IDLE
Q2 TRIGGER EVENT
Q1 COMPLETE
Q1 PAUSE BIT SET
Q2 PAUSE BIT SET
Q1 COMPLETE
Q2 TRIGGER
Q1 TRIGGER EVENT
Q1 ACTIVE/
PENDING
Q2 TRIGGER EVENT
Q1 PAUSE BIT SET
Q1 PAUSED/
Q2 ACTIVE
Queued Analog-to-Digital Converter (QADC)
DELAYED TRANSITION
Q1 ACTIVE/
Q2 IDLE
Q1 TRIGGER EVENT
(TEMPORARY)
Q2 TRIGGER
Q1 PAUSED/
PENDING
Q1 PAUSE BIT SET
Q2 COMPLETE
Register Descriptions
Advance Information
Q1 PAUSED/
Q2 IDLE
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