MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 245
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11.4 Modes of Operation
11.4.1 Normal PLL Mode
11.4.2 1:1 PLL Mode
11.4.3 External Clock Mode
11.4.4 Low-Power Options
11.4.4.1 Wait and Doze Modes
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The clock module can be operated in normal PLL mode (default), 1:1
PLL mode, or external clock mode.
In normal PLL mode, the PLL is fully programmable. It can synthesize
frequencies ranging from 2x to 9x the reference frequency and has a
post divider capable of reducing this synthesized frequency without
disturbing the PLL. The PLL reference can be either a crystal oscillator
or an external clock.
In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external
clock input reference frequency. The post divider is not active.
In external clock mode, the PLL is bypassed, and the external clock is
applied to EXTAL. The resulting operating frequency is one-half the
external clock frequency.
During wakeup from a low-power mode, the FLASH clock always clocks
through at least 16 cycles before the CPU clocks are enabled. This
allows the FLASH module time to recover from the low-power mode, and
software can immediately resume fetching instructions from the
memory.
In wait and doze modes, the system clocks to the peripherals are
enabled, and the clocks to the CPU, FLASH, and SRAM are stopped.
Each module can disable the module clocks locally at the module level.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Clock Module
Advance Information
Modes of Operation
Clock Module
flash
245
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