MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 532

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

External Bus Interface Module (EBI)
20.3.12 Transfer Size (TSIZ[1:0])
20.3.13 Processor Status (PSTAT[3:0])
20.4 Memory Map and Registers
20.5 Operand Transfer
Advance Information
532
TSIZ[1:0] provides an indication of the M•CORE transfer size. See
20-2. This function is enabled by default in master mode and emulation
mode, and disabled by default in single-chip mode. Selection of this
function is through the Chip Configuration Register (see
Configuration
as pins INT7 and INT6 of the EPORT module.
PSTAT[3:0] provides an indication of the M•CORE processor status.
See
default in emulation mode, and disabled by default in master mode and
single-chip mode. Selection of this function is through the Chip
Configuration Register. When this feature is disabled, these pins act as
pins INT5, INT4, INT3, and INT2 of the EPORT module.
The EBI is not memory-mapped and has no software-accessible
registers.
The possible operand accesses for the internal M•CORE bus are:
No misaligned transfers are supported. The EBI controls the byte,
half-word, or word operand transfers between the M•CORE bus and a
16-bit or 32-bit port. “Port” refers to the width of the data path that an
external device uses during a data transfer. Each port is assigned to
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Freescale Semiconductor, Inc.
Table 20-6
For More Information On This Product,
Byte
Aligned upper half-word
Aligned lower half-word
Aligned word
External Bus Interface Module (EBI)
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Register). When this feature is disabled, these pins act
for status indication codes. This function is enabled by
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4.7.3.1 Chip
MOTOROLA
Table