MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 214
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Second Generation FLASH for M•CORE (SGFM)
Advance Information
214
NOTE:
In emulation mode, writes to the SGFM array will generate an SGFM
access error and set the ACCERR bit (see
Illegal
LOCK — Write Lock Control Bit
CBEIE — Command Buffer Empty Interrupt Enable Bit
CCIE — Command Complete Interrupt Enable Bit
KEYACC — Enable Security Key Writing Bit
SGFM array. Instead, external memory that emulates the FLASH
must drive the data bus, and the EBI emulation chip select
mechanism terminates the bus cycle instead of the SGFM.
The LOCK bit is always readable but can only be set once in user
mode. In debug or test mode, the LOCK bit is always writable.
The CBEIE bit is readable and writable in all modes. CBEIE enables
an interrupt request when the command buffer for the FLASH
physical blocks selected by BKSEL[1:0] is empty.
The CCIE bit is readable and writable in all modes. CCIE enables an
interrupt when the command executing for the FLASH physical blocks
selected by BKSEL[1:0] is complete.
The KEYACC bit is readable in all modes and only writable if the
KEYEN bit in the SGFMSEC register is set.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
1 = Emulation mode
0 = User mode
1 = The EME bit, SGFMPROT, SGFMSACC, and SGFMDACC
0 = The EME bit, SGFMPROT, SGFMSACC, and SGFMDACC
1 = Request an interrupt whenever the CBEIF flag is set.
0 = Command buffer empty interrupts disabled
1 = Request an interrupt whenever the CCIF flag is set.
0 = Command complete interrupts disabled
1 = Writes to the FLASH array are interpreted as keys to open the
0 = Writes to the FLASH array are interpreted as the start of a
Operations).
registers are write-locked
registers are writable
back door.
program, erase, or verify sequence.
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
10.8.3.4 FLASH User Mode
MOTOROLA
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