MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 464

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Queued Analog-to-Digital Converter (QADC)
Advance Information
464
NOTE:
Address: 0x00ca_0200 through 0x00ca_027e
Reset:
Reset:
Read:
Read:
Write:
Write:
Read: Anytime except reads during stop mode are invalid
Write: Anytime except during stop mode
P — Pause Bit
The P bit does not cause the queue to pause in the software. Initiated
modes or externally gated modes.
BYP — Sample Amplifier Bypass Bit
The pause bit allows subqueues to be created within queue 1 and
queue 2. The QADC performs the conversion specified by the CCW
with the pause bit set and then the queue enters the pause state.
Another trigger event causes execution to continue from the pause to
the next CCW.
Setting BYP in a CCW enables the amplifier bypass mode for a
conversion and subsequently changes the timing. The initial sample
time is eliminated, reducing the potential conversion time by two
QCLKs. However, due to internal RC effects, a minimum final sample
time of four QCLKs must be allowed. When using this mode, the
Freescale Semiconductor, Inc.
Figure 19-14. Conversion Command Word Table (CCW)
U = Unaffected
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enter pause state after execution of current CCW.
0 = Do not enter pause state after execution of current CCW.
Bit 15
Bit 7
IST1
U
0
0
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= Writes have no effect and the access terminates without a transfer error exception.
IST0
14
U
0
0
6
CHAN5
13
U
0
0
5
CHAN4
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
U
0
0
4
CHAN3
11
U
0
0
3
CHAN2
10
U
0
0
2
CHAN1
P
U
U
9
1
MOTOROLA
CHAN0
Bit 8
BYP
Bit 0
U
U