MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 517

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MMC2114CFCAG33

Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Datasheets

Specifications of MMC2114CFCAG33

Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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19.11.5 Accommodating Positive/Negative Stress Conditions
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Other suggestions for PCB layout in which the QADC is employed
include:
Positive or negative stress refers to conditions which exceed nominally
defined operating limits. Examples include applying a voltage exceeding
the normal limit on an input (for example, voltages outside of the
suggested supply/reference ranges) or causing currents into or out of
the pin which exceed normal limits. QADC specific considerations are
voltages greater than V
which cause excessive currents into or out of the input. Refer to
Table 23-6. QADC Absolute Maximum Ratings
QADC Electrical Specifications (Operating)
exact magnitudes.
Either stress conditions can potentially disrupt conversion results on
neighboring inputs. Parasitic devices, associated with CMOS
processes, can cause an immediate disruptive influence on neighboring
pins. Common examples of parasitic devices are diodes to substrate and
bipolar devices with the base terminal tied to substrate (V
ground). Under stress conditions, current injected on an adjacent pin can
cause errors on the selected channel by developing a voltage drop
across the selected channel’s impedances.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Analog ground must be low impedance to all analog ground points
in the circuit.
Bypass capacitors should be as close to the power pins as
possible.
The analog ground should be isolated from the digital ground. This
can be done by cutting a separate ground plane for the analog
ground.
Non-minimum traces should be utilized for connecting bypass
capacitors and filters to their corresponding ground/power points.
Minimum distance for trace runs when possible.
Go to: www.freescale.com
DDA
or less than V
Queued Analog-to-Digital Converter (QADC)
SSA
applied to an analog input
Pin Connection Considerations
for more information on
and
Advance Information
Table 23-7.
SS
/V
SSA
517

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