MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 192
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Interrupt Controller Module
8.8.1 Interrupt Sources and Prioritization
8.8.2 Fast and Normal Interrupt Requests
Advance Information
192
Each interrupt source in the system sends a unique signal to the interrupt
controller. Up to 40 interrupt sources are supported. Each interrupt
source can be programmed to one of 32 priority levels by programing the
PLS bits of the PLSR in the interrupt controller. The highest priority level
is 31 and lowest priority level is 0. By default, each interrupt source is
assigned to the priority level 0. Each interrupt source is associated with
a 5-bit priority level select value that selects one of 32 priority levels. The
interrupt controller uses the priority levels as the basis for the generation
of all interrupt signals to the CPU.
Interrupt requests may be forced by software by writing to IFRH and
IFRL. Each bit of IFRH and IFRL is logically ORed with the
corresponding interrupt source signal before the priority level select
logic. To negate the forced interrupt request, the interrupt handler can
clear the appropriate IFR bit. IPR reflects the state of each priority level.
FIER allows individual enabling or masking of pending fast interrupt
requests. FIER is logically ANDed with IPR, and the result is stored in
FIPR. FIPR bits are bit-wise ORed together and inverted to form the fast
interrupt signal routed to the CPU (see
software to quickly determine the highest priority pending fast interrupt.
The output of FIPR also feeds into a 32-to-5 priority encoder to generate
the vector number to present to the CPU if vectored interrupts are
required.
NIER allows individual enabling or masking of pending normal interrupt
requests. NIER is logically ANDed with IPR, and the result is stored in
NIPR. NIPR bits are bit-wise ORed together and inverted to form the
normal interrupt signal routed to the CPU. The normal interrupt signal is
only asserted if the fast interrupt signal is negated. The NIPR allows
software to quickly determine the highest priority pending normal
interrupt. The output of NIPR also feeds into a 32-to-5 priority encoder to
generate the vector number to present to the CPU if vectored interrupts
are required. If the fast interrupt signal is asserted, then the vector
number is determined by the highest priority fast interrupt.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Interrupt Controller Module
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
Figure
8-1). The FIPR allows
MOTOROLA
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