MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 281

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.5 Functional Description
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The initial pin function is determined during reset configuration (see
Section 4. Chip Configuration Module
registers (PCDPAR and PEPAR) allow the user to select between digital
I/O or another pin function after reset.
In single-chip mode, all pins are configured as digital I/O by default.
Every digital I/O pin is individually configurable as an input or an output
via a data direction register (DDRx).
Every port has an output data register (PORTx) and a pin data register
(PORTxP/SETx) to monitor and control the state of its pins. Data written
to PORTx is stored and then driven to the corresponding PORTx pins
configured as outputs.
Reading PORTx returns the current state of the register regardless of
the state of the corresponding pins.
Reading PORTxP returns the current state of the corresponding pins,
regardless of whether the pins are input or output.
Every port has a set register (PORTxP/SETx) and a clear register
(CLRx) for setting or clearing individual bits in PORTx.
In master mode and emulation mode, ports A and B function as the
upper external data bus, D[31:16]. When the PCDPA bit is set, ports C
and D function as the lower external data bus, D[15:0]. Ports E–I are
configured to support external memory and emulation functions.
In master mode, the function of EB[3:2] is determined by the PCDPA bit.
The function of CS[3:0] is determined by the individual chip select enable
(CSENx) bits.
Freescale Semiconductor, Inc.
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Ports Module
(CCM)). The pin assignment
Functional Description
Advance Information
Ports Module
281