MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 470
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
19.8.8.3 Left-Justified Unsigned Result Register (LJURR)
19.9 Functional Description
19.9.1 Result Coherency
Advance Information
470
Address: 0x00ca_0380 through 0x00ca_03fe
Reset:
Reset:
Read:
Read:
Write:
Write:
RESULT[15:6] — Result Field
This subsection provides a functional description of the QADC.
The QADC supports byte and half-word reads and writes across a 16-bit
data bus interface. All conversion results are stored in half-word
registers, and the QADC does not allow more than one result register to
be read at a time. For this reason, the QADC does not guarantee read
coherency.
Specifically, this means that while the QADC is operating, the data in the
result registers can change from one read to the next. Simply initiating a
read of one result register will not prevent another from being updated
with a new conversion result.
Thus, to read any given number of result registers coherently, the queue
or queues capable of modifying these registers must be inactive. This
can be guaranteed by system operating conditions (such as, known
completion of a software-initiated queue single-scan or no possibility of
an externally triggered/gated queue scan) or by simply disabling the
queues (writing MQ1 and/or MQ2 to 0).
Figure 19-17. Left-Justified Unsigned Result Register (LJURR)
The conversion result is unsigned, left-justified data.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Bit 15
Bit 7
RESULT
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
14
6
13
5
0
0
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
12
4
0
0
RESULT
11
3
0
0
10
2
0
0
9
1
0
0
MOTOROLA
Bit 8
Bit 0
0
0
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