MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 269

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.8.6.3 Voltage Control Output (VCO)
11.8.6.4 Multiplication Factor Divider (MFD)
11.9 Reset
11.10 Interrupts
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The UP and DOWN signals from the PFD control whether the charge
pump applies or removes charge, respectively, from the loop filter. The
filter is integrated on the chip.
The voltage across the loop filter controls the frequency of the VCO
output. The frequency-to-voltage relationship (VCO gain) is positive, and
the output frequency is four times the target system frequency.
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the
VCO and feeds it back to the PFD. The PFD controls the VCO frequency
via the charge pump and loop filter such that the reference and feedback
clocks have the same frequency and phase. Thus, the frequency of the
input to the MFD, which is also the output of the VCO, is the reference
frequency multiplied by the same amount that the MFD divides by. For
example, if the MFD divides the VCO frequency by six, the PLL is
frequency locked when the VCO frequency is six times the reference
frequency. The presence of the MFD in the loop allows the PLL to
perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication
factor is one.
The clock module can assert a reset when a loss of clock or loss of lock
occurs as described in
Reset initializes the clock module registers to a known startup state as
described in
The clock module does not generate interrupt requests.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
11.7 Memory Map and
Clock Module
11.8 Functional
Registers.
Description.
Advance Information
Clock Module
Reset
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