MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 431
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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19.5.2 Stop Mode
19.6 Signals
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Although the QADC saves a pointer to the next CCW in the current
queue, software can force the QADC to execute a different CCW by
reconfiguring the QADC. When the QADC exits debug mode, it looks at
the queue operating modes, the current queue pointer, and any pending
trigger events to decide which CCW to execute.
The QADC enters a low-power idle state whenever the QSTOP bit is set
or the CPU enters low-power stop mode.
QADC stop:
Because the bias currents to the analog circuit are turned off in stop
mode, the QADC requires some recovery time (t
analog circuits.
The QADC uses the external pins shown in
channel/port pins that can support up to 18 channels when external
multiplexing is used (including internal channels). All of the channel pins
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Disables the analog-to-digital converter, effectively turning off the
analog circuit
Aborts the conversion sequence in progress
Makes the Data Direction Register (DDRQA), Port Data Registers
(PORTQA and PORTQB), Control Registers (QACR2, QACR1,
and QACR0) and the Status Registers (QASR1 and QASR0)
read-only. Only the Module Configuration Register (QADCMCR)
remains writable.
Makes the RAM inaccessible, so that valid data cannot be read
from RAM (result word table and CCW) or written to RAM (result
word table and CCW)
Resets QACR1, QACR2, QASR0, and QASR1
Holds the QADC periodic/interval timer in reset
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Figure
SR
19-2. There are eight
) to stabilize the
Advance Information
Signals
431
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