MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 379

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
Serial Communications Interface Modules (SCI1 and SCI2)
and SCIDRL can accept new data. If the TIE bit is set, TDRE generates
an interrupt request.
SCIDRH and SCIDRL transfer data to the transmit shift register and sets
TDRE 9/16ths of a bit time after the previous frame’s stop bit starts to
shift out.
Hardware supports odd or even parity. When parity is enabled, the most
significant data bit is the parity bit.
When the transmit shift register is not transmitting a frame, the TXD pin
goes to the idle condition, logic 1. Clearing the TE bit while the
transmitter is idle will return control of the TXD pin to the SCI data
direction (SCIDDR) and SCI port (SCIPORT) registers.
If the TE bit is cleared while a transmission is in progress (while TC = 0),
the frame in the transmit shift register continues to shift out. Then the
TXD pin reverts to being a general-purpose I/O pin even if there is data
pending in the SCI Data Register. To avoid accidentally cutting off a
message, always wait until TDRE is set after the last frame before
clearing TE.
To separate messages with preambles with minimum idle line time, use
this sequence between messages:
When the SCI relinquishes the TXD pin, the SCIPORT and SCIDDR
registers control the TXD pin.
To force TXD high when turning off the transmitter, set bit 1 of the SCI
Port Register (SCIPORT) and bit 1 of the SCI Data Direction Register
(SCIDDR). The TXD pin goes high as soon as the SCI relinquishes
control of it. See
Direction
1. Write the last byte of the first message to SCIDRH and SCIDRL.
2. Wait until the TDRE flag is set, indicating the transfer of the last
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the first byte of the second message to SCIDRH and
Freescale Semiconductor, Inc.
For More Information On This Product,
frame to the transmit shift register.
SCIDRL.
Register.
Go to: www.freescale.com
17.7.8 SCI Port Data Register
Serial Communications Interface Modules (SCI1 and SCI2)
and
17.7.9 SCI Data
Advance Information
Transmitter
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