MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 215
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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10.7.1.2 SGFM Clock Divider Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00d0_0002
BKSEL[1:0] — Register Bank Select Field
Table 10-3
BKSEL field depending on the size of the FLASH memory array.
The SGFM Clock Divider Register (SGFMCLKD) is unbanked and is
used to set the frequency of the clock used for timed events in program
and erase algorithms.
In user mode, all bits in SGFMCLKD are readable while bits 6–0 can only
be written once. In test and debug modes, all bits in SGFMCLKD are
readable and writable at anytime, except bit 7 which is a status-only bit
and is not writable in any mode.
Reset:
Read:
Write:
The BKSEL bits are readable and writable in all modes and select
which set of bank registers is accessible.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
Figure 10-4. SGFM Clock Divider Register (SGFMCLKD)
For More Information On This Product,
BKSEL[1:0]
DIVLD
Bit 7
0
00
01
10
11
shows which set of banked registers is selected by the
Go to: www.freescale.com
Table 10-3. Register Bank Select Decoding
= Reserved
PRDIV
6
0
128 Kbytes
Bank 0
Bank 0
Bank 0
Bank 0
DIV5
5
0
Second Generation FLASH for M•CORE (SGFM)
256 Kbytes
Bank 0
Bank 1
Bank 0
Bank 1
DIV4
4
0
DIV3
3
0
384 Kbytes
Bank 0
Bank 1
Bank 2
Bank 2
DIV2
2
0
Module Memory Map
Advance Information
512 Kbytes
DIV1
Bank 0
Bank 1
Bank 2
Bank 3
1
0
DIV0
Bit 0
0
215
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