MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 492
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Queued Analog-to-Digital Converter (QADC)
19.10.2 Boundary Conditions
Advance Information
492
NOTE:
The queue operation boundary conditions are:
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in QADC behavior. For example, if BQ2 is
set to CCW0, CCW0 contains the EOQ code, and a trigger event occurs
on queue 1, the QADC reads CCW0 and detects both end-of-queue
conditions. The completion flag is set and queue 1 becomes idle.
Boundary conditions also exist for combinations of pause and
end-of-queue. One case is when a pause bit is in one CCW and an
end-of-queue condition is in the next CCW. The conversion specified by
the CCW with the pause bit set completes normally. The pause flag is
set. However, because the end-of-queue condition is recognized, the
completion flag is also set and the queue status becomes idle, not
paused. Examples of this situation include:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
The first CCW in a queue specifies channel 63, the end-of-queue
(EOQ) code. The queue becomes active and the first CCW is
read. The end-of-queue is recognized, the completion flag is set,
and the queue becomes idle. A conversion is not performed.
BQ2 (beginning of queue 2) is set at the end of the CCW table (63)
and a trigger event occurs on queue 2. The end-of-queue
condition is recognized, a conversion is performed, the completion
flag is set, and the queue becomes idle.
BQ2 is set to CCW0 and a trigger event occurs on queue 1. After
reading CCW0, the end-of-queue condition is recognized, the
completion flag is set, and the queue becomes idle. A conversion
is not performed.
BQ2 (beginning of queue 2) is set beyond the end of the CCW
table (64–127) and a trigger event occurs on queue 2. The
end-of-queue condition is recognized immediately, the completion
flag is set, and the queue becomes idle. A conversion is not
performed.
The pause bit is set in CCW5 and the channel 63 (EOQ) code is
in CCW6.
The pause is in CCW63.
During queue 1 operation, the pause bit is set in CCW20 and BQ2
points to CCW21.
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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