MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 389
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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17.12.5.2 Fast Data Tolerance
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Serial Communications Interface Modules (SCI1 and SCI2)
Figure 17-24
without causing a noise error or a framing error. The fast stop bit ends at
RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
For 8-bit data, sampling of the stop bit takes the receiver:
With the misaligned data shown in
154 RT cycles at the point when the count of the transmitting device is:
The maximum percent difference between the receiver count and the
transmitter count for fast 8-bit data with no errors is:
For 9-bit data, sampling of the stop bit takes the receiver:
With the misaligned data shown in
170 RT cycles at the point when the count of the transmitting device is:
The maximum percent difference between the receiver count and the
transmitter count for fast 9-bit data with no errors is:
Freescale Semiconductor, Inc.
RECEIVER
RT CLOCK
For More Information On This Product,
10 bit times
9 bit times
Go to: www.freescale.com
10 bit times
11 bit times
shows how much a fast received frame can be misaligned
16 RT cycles + 10 RT cycles = 154 RT cycles.
16 RT cycles + 10 RT cycles = 170 RT cycles.
Serial Communications Interface Modules (SCI1 and SCI2)
154 160
------------------------- -
170 176
------------------------- -
Figure 17-24. Fast Data
STOP
154
170
–
–
16 RT cycles = 160 RT cycles.
16 RT cycles = 176 RT cycles.
Figure
Figure
100
100
SAMPLES
DATA
=
=
17-24, the receiver counts
17-24, the receiver counts
3.90%
3.53%
IDLE OR NEXT FRAME
Advance Information
Receiver
389
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