MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 509
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
MMC2114CFCAG33
Manufacturer:
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MMC2114CFCAG33
Manufacturer:
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19.10.11 Result Word Table
19.11 Pin Connection Considerations
19.11.1 Analog Reference Pins
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
The result word table is a 64 half-word (128 byte) long by 10-bit wide
RAM. An entry is written by the QADC after completing an analog
conversion specified by the corresponding CCW table entry. The result
word table can be read or written, but in normal operation is only read to
obtain analog conversions from the QADC. Unimplemented bits read as
0s and writes have no effect.
Although the result RAM can be written, some write operations, like bit
manipulation, may not operate as expected because the hardware
cannot access a true 16-bit value.
While there is only one result word table, the half-word (16-bit) data can
be accessed in three different data formats:
The left justified, signed format corresponds to a half-scale, offset binary,
two’s complement data format. The address used to read the result table
determines the data alignment format. All write operations to the result
word table are right justified.
The QADC requires accurate, noise-free input signals for proper
operation. This section discusses the design of external circuitry to
maximize QADC performance.
No A/D converter can be more accurate than its analog reference. Any
noise in the reference can result in at least that much error in a
conversion. The reference for the QADC, supplied by pins V
should be low-pass filtered from its source to obtain a noise-free, clean
signal. In many cases, simple capacitive bypassing may suffice. In
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Right justified with 0s in the higher order unused bits
Left justified with the most significant bit inverted to form a sign bit,
and 0s in the unused lower order bits
Left justified with 0s in the lower order unused bits
Go to: www.freescale.com
Queued Analog-to-Digital Converter (QADC)
Pin Connection Considerations
Advance Information
RH
and V
RL
509
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