MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 485

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Q1:
Q2:
QS:
IDLE
0000
IDLE
Situation S5
events are detected while queue 1 is busy, the trigger overrun error bit
is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the
same when the pause feature is used for either queue.
The remaining situations, S6 through S11, show the impact of a queue 1
trigger event occurring during queue 2 execution. Because queue 1 has
higher priority, the conversion taking place in queue 2 is aborted so that
there is no variable latency time in responding to queue 1 trigger events.
In situation 6
CCW in queue 2 is aborted just before the conversion is complete, so
that queue 1 execution can begin. Queue 2 is considered suspended.
After queue 1 is finished, queue 2 starts over with the first CCW, when
the RESUME control bit is set to 0. Situation S7
that when pause operation is not used with queue 2, queue 2
suspension works the same way.
Freescale Semiconductor, Inc.
Q1:
Figure 19-27. CCW Priority Situation 5
For More Information On This Product,
Q2:
Queued Analog-to-Digital Converter (QADC)
T1
1000
C1
ACTIVE
T2
TOR2
TRIG
1011
C2
T2
Go to: www.freescale.com
(Figure
(Figure
PF1
C1
ACTIVE
0110
PAUSE
19-27) shows that when multiple queue 2 trigger
C2
19-28), the conversion initiated by the second
PF2
0101
PAUSE
T1
1001
C3
ACTIVE
ACTIVE
T2
Queued Analog-to-Digital Converter (QADC)
TOR2
1011
TRIG
C4
T2
CF1
C3
ACTIVE
0010
C4
CF2
(Figure
IDLE
Advance Information
IDLE
0000
19-29) shows
Digital Control
485