MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 258
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Clock Module
11.8 Functional Description
11.8.1 System Clock Modes
Advance Information
258
CAUTION:
This subsection provides a functional description of the clock module.
The system clock source is determined during reset (see
Configuration During
reset and is of no importance after reset is negated. If PLLEN is changed
during a reset other than power-on reset, the internal clocks may glitch
as the clock source is changed between external clock mode and PLL
clock mode. Whenever PLLEN is changed in reset, an immediate loss of
lock condition occurs.
Table 11-6
relationships for the possible clock modes.
XTAL must be tied low in external clock mode when reset is asserted. If
it is not, clocks could be suspended indefinitely.
The external clock is divided by two internally to produce the system
clocks.
1. f
Normal PLL clock mode
1:1 PLL clock mode
External clock mode
Freescale Semiconductor, Inc.
f
MFD ranges from 0 to 7.
RFD ranges from 0 to 7.
ref
sys
For More Information On This Product,
= input reference frequency
= CLKOUT frequency
Table 11-6. Clock-Out and Clock-In Relationships
Clock Mode
shows the clock-out frequency to clock-in frequency
Go to: www.freescale.com
Clock Module
Reset). The value of PLLEN is latched during
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
f
f
f
Ã
sys
sys
sys
= f
= f
= f
ref
ref
ref
/2
(MFD + 2)/2
PLL Options
RFD
(1)
Table 4-7.
MOTOROLA
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