MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 111

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4.4 Serial Communications Interface (SCI1 and SCI2) Pin Functions
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
GPIO [7:4] of SPI module not implemented.
The default reset values for the PUPSP bit in SPIPURD is 0. Thus, the
pullup function is disabled by default.
Full SCI interface capabilities and GPIO functions using the TXD1/2 and
RXD1/2 pins are supported.
GPIO [7:2] of SCI modules not implemented.
The default reset value for PUPSCI is 0. Thus, the pullup function is
disabled by default.
Only the pins associated with each SCI are controlled by the register bits
for the corresponding SCI. Thus, the WOMS register bit from SCI1 only
affects TXD1 and RXD1 and has no effect on TXD2 and RXD2.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Writes to bits [7:4] of the SPIPORT and SPIDDR registers have no
effect except to change the register bit values.
Reads of bits [7:4] of the SPIPORT when the corresponding
SPIDDR bits are set for inputs always return 0.
PUPSP and RDPSP register bits have no effect.
WOMS register bit controls whether output buffers behave as
open-drain outputs. Default is not open-drain outputs.
PUPSCI register bit enables internal weak pad pullup devices.
Default is pullups disabled.
RDPSCI register bit controls reduced drive function of output
buffers. Default is full drive.
Writes to bits [7:2] of the SCIPORT and SCIDDR registers have
no effect except to change the register bit values.
Reads of bits [7:2] of the SCIPORT when the corresponding
SCIDDR bits are set for inputs always return 0.
PUPSCI and RDPSCI register bits have no effect.
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Signal Description
Chip Specific Implementation Signal Issues
Advance Information
Signal Description
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