MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 567
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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22.5 Instruction Shift Register
22.5.1 EXTEST Instruction
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
The top-level TAP module uses a 4-bit Instruction Shift Register with no
parity. This register transfers its value to a parallel hold register and
applies an instruction on the falling edge of TCLK when the TAP state
machine is in the update-IR state. To load the instructions into the shift
portion of the register, place the serial data on the TDI pin prior to each
rising edge of TCLK. The MSB of the instruction shift register is the bit
closest to the TDI pin and the LSB is the bit closest to the TDO pin.
Table 22-1
IR3–IR0. The last three instructions in the table are reserved for
manufacturing purposes only.
Unused opcodes are currently decoded to perform the BYPASS
operation, but Motorola reserves the right to change their decodings in
the future.
The external test instruction (EXTEST) selects the Boundary Scan
Register. The EXTEST instruction forces all output pins and bidirectional
pins configured as outputs to the preloaded fixed values (with the
SAMPLE/PRELOAD instruction) and held in the boundary-scan update
registers. The EXTEST instruction can also configure the direction of
bidirectional pins and establish high-impedance states on some pins.
EXTEST also asserts internal reset for the system logic to force a
predictable internal state while performing external boundary scan
operations.
Freescale Semiconductor, Inc.
For More Information On This Product,
JTAG Test Access Port and OnCE
lists the instructions supported along with their opcodes,
Go to: www.freescale.com
JTAG Test Access Port and OnCE
Instruction Shift Register
Advance Information
567
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