MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 449

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
PIE2 — Queue 2 Pause Software Interrupt Enable Bit
SSE2 — Queue 2 Single-Scan Enable Bit
MQ2[12:8] — Queue 2 Operating Mode Field
PIE2 enables an interrupt request when queue 2 enters the pause
state. The interrupt request is initiated when conversion is complete
for a CCW that has the pause bit set.
SSE2 enables a single-scan of queue 2 after a trigger event occurs.
SSE2 may be set during the same write cycle that sets the MQ2 bits
for one of the single-scan queue operating modes. The single-scan
enable bit can be written to 1 or 0, but is always read as a 0, unless
the QADC is in test mode. The QADC clears SSE2 when the
single-scan is complete.
The MQ2 field selects the operating mode for queue 2.
Table 19-5
queue 2 operating modes.
Freescale Semiconductor, Inc.
MQ2[12:8]
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
1 = Enable the queue 2 pause interrupt.
0 = Disable the queue 2 pause interrupt.
1 = Allow a trigger event to start queue 2 in a single-scan mode.
0 = Trigger events are ignored for queue 2 single-scan modes.
00000
00001
00010
00100
00101
01000
01001
00011
00110
00111
Go to: www.freescale.com
shows the bits in the MQ2 field which enable different
Table 19-5. Queue 2 Operating Modes
Externally triggered falling edge single-scan mode
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE2)
Externally triggered rising edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Queued Analog-to-Digital Converter (QADC)
Operating Modes
Register Descriptions
Advance Information
7
8
9
10
11
12
449