MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 378

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Communications Interface Modules (SCI1 and SCI2)
17.11.2 Transmitting a Frame
Advance Information
378
Serial Communications Interface Modules (SCI1 and SCI2)
To begin an SCI transmission:
Writing the TE bit from 0 to 1 loads the transmit shift register with a
preamble of 10 (if M = 0) or 11 (if M = 1) logic 1s. When the preamble
shifts out, the SCI transfers the data from SCIDRH and SCIDRL to the
transmit shift register. The transmit shift register prefaces the data with
a 0 start bit and appends the data with a 1 stop bit and begins shifting
out the frame.
The SCI sets the TDRE flag every time it transfers data from SCIDRH
and SCIDRL to the transmit shift register. TDRE indicates that SCIDRH
1. Configure the SCI:
2. Transmit a byte:
3. Repeat step 2 for each subsequent transmission.
Freescale Semiconductor, Inc.
For More Information On This Product,
a. Write a baud rate value to SCIBDH and SCIBDL.
b. Write to SCICR1 to:
a. Clear the TDRE flag by reading SCISR1 and, if sending 9-bit
b. Write the byte to be transmitted (or low-order 8 bits if sending
c. Write to SCICR2 to:
data, write the ninth data bit to SCDRH.
9-bit data) to SCIDRL.
vi. Enable or disable the parity function and select odd or
iii. Select 10-bit or 11-bit frames
iv. Select the receiver wakeup condition: address mark or
iii. Enable or disable the receiver
iv. Put the receiver in standby if required
ii. Select open-drain or wired-OR SCI outputs
ii. Enable the transmitter and queue a break frame
v. Select idle line type
i. Enable or disable loop mode and select the receiver
i. Enable or disable TDRE, TC, RDRF, and IDLE interrupt
Go to: www.freescale.com
feedback path
idle line
even parity
requests
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
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