MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 110
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Signal Description
3.4.2 INT Signal Functions
3.4.3 Serial Peripheral Interface (SPI) Pin Functions
Advance Information
110
NOTE:
The INT signals have these multiple functions:
If the SZEN or PSTEN bits are set during emulation mode, then the
corresponding edge port INT functions are lost and will not be emulated
externally.
The default reset value for the PUPSC1 bit in SCIPURD is 0. Thus, the
pullup function is disabled by default.
The SPI module can support up to eight external pins, but only the four
pins required for the SPI interface are implemented.
Full SPI interface capabilities and GPIO functions using the MISO,
MOSI, SCK, and SS pins are supported.
•
•
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
If the SZEN bit in the Chip Configuration Register is set, then
INT[7:6] will be used to reflect the state of the TSIZ[1:0] signals
from the CPU. See
If the PSTEN bit in the Chip Configuration Register (CCR) is set,
then INT[5:2] will be used to reflect the state of the PSTAT[3:0]
signals from the CPU. See
SWOM register bit controls whether output buffers behave as
open-drain outputs. Default is not open-drain outputs.
PUPSP0 register bit enables internal weak pad pullup devices.
Default is pullups disabled.
RDPSP0 register bit controls reduced drive function of output
buffers. Default is full drive.
Go to: www.freescale.com
Signal Description
4.7.3.1 Chip Configuration
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
4.7.3.1 Chip Configuration
Register.
MOTOROLA
Register.
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