MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 591
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
SQC1 and SQC0 — Sequential Control Field
DR — Debug Request Bit
and SQC0
The SQC field allows memory breakpoint B and trace occurrences to
be suspended until a qualifying event occurs. Test logic reset clears
the SQC field. See
DR requests the CPU to enter debug mode unconditionally. The PM
bits in the OnCE Status Register indicate that the CPU is in debug
mode. Once the CPU enters debug mode, it returns there even with
a write to the OCMR with GO and EX set until the DR bit is cleared.
Test logic reset clears the DR bit.
Freescale Semiconductor, Inc.
SQC1
00
01
10
11
For More Information On This Product,
JTAG Test Access Port and OnCE
Table 22-5. Sequential Control Field Settings
Disable sequential control operation. Memory breakpoints and trace
Suspend normal trace counter operation until a breakpoint condition
Qualify memory breakpoint B matches with a breakpoint occurrence
Combine the 01 and 10 qualifications. In this mode, no breakpoint
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operation are unaffected by this field.
occurs for memory breakpoint B. In this mode, memory breakpoint B
occurrences no longer cause breakpoint requests to be generated.
Instead, trace counter comparisons are suspended until the first
memory breakpoint B occurrence. After the first memory breakpoint
B occurrence, trace counter control is released to perform normally,
assuming TME is set. This allows a sequence of breakpoint
conditions to be specified prior to trace counting.
for memory breakpoint A. In this mode, memory breakpoint A
occurrences no longer cause breakpoint requests to be generated.
Instead, memory breakpoint B comparisons are suspended until the
first memory breakpoint A occurrence. After the first memory
breakpoint A occurrence, memory breakpoint B is enabled to
perform normally. This allows a sequence of breakpoint conditions
to be specified.
requests are generated, and trace count operation is enabled once
a memory breakpoint B occurrence follows a memory breakpoint A
occurrence if TME is set.
Table
22-5.
Meaning
JTAG Test Access Port and OnCE
Functional Description
Advance Information
591
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