MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 233

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
NOTE:
NOTE:
This three-step command write sequence must be strictly followed. No
intermediate writes to the SGFM module are permitted between these
three steps. The command write sequence is:
The page erase command operates simultaneously on adjacent erase
pages in two interleaved FLASH physical blocks. Thus, a single erase
page is effectively 1 Kbyte.
On devices with 256 Kbytes of FLASH or more, concurrent command
execution is possible. After a command is launched for the FLASH
physical blocks serviced by the current set of banked registers,
BKSEL[1:0] can be changed in order to launch a command for another
pair of FLASH physical blocks. A command launched for one pair of
FLASH physical blocks will not interfere with the execution of commands
launched for other FLASH physical blocks and will only set the CCIF flag
in the SGFMUSTAT register selected by BKSEL[1:0] at the time the
command was launched.
The FLASH state machine will flag errors in command write sequences
by means of the ACCERR and PVIOL flags in the SGFMUSTAT register.
An erroneous command write sequence will self-abort and set the
appropriate flag. The ACCERR or PVIOL flags must be cleared before
commencing another command write sequence.
1. Write the 32-bit word to be programmed to its location in the
2. Write the program, erase, or verify command to SGFMCMD, the
3. Launch the command by writing a 1 to the CBEIF flag. This will
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
SGFM array. The address and data will be stored in internal
buffers. All address bits are valid for program commands. The
value of the data written for verify and erase commands is ignored.
For mass erase or verify, the address can be any location in the
SGFM array. For page erase, address bits [9:0] are ignored.
command buffer. See
Commands.
clear CBEIF. When command execution is complete, the FLASH
state machine will set the CCIF flag. The CBEIF flag will also be
set again, indicating that the address, data, and command buffers
are ready for a new command sequence to begin.
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10.8.3.3 FLASH User Mode Valid
Second Generation FLASH for M•CORE (SGFM)
Advance Information
SGFM User Mode
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