MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 232

• Manufacturer Part Number: MMC2114CFCAG33
• Description: IC MCU 32BIT 33MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCorer

Specifications of MMC2114CFCAG33

• Core Processor: M210
• Core Size: 32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: MMC2114
• Core: M-CORE
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 33 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Controller Family/series: MCORE
• No. Of I/o's: 104
• Ram Memory Size: 32KB
• Cpu Speed: 33MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Second Generation FLASH for M•CORE (SGFM)
10.8.3.2 Program, Erase, and Verify Sequences
Advance Information
232
WARNING:
NOTE:
Consider the following example for f
So, for f
196.43 kHz which is a valid frequency for the timing of program and
erase operations.
For proper program and erase operations, it is critical to set FCLK
between 150 kHz and 200 kHz. Array damage due to overstress can
occur when FCLK is less than 150 kHz. Incomplete programming
and erasure can occur when FCLK is greater than 200 kHz.
Command execution time increases proportionally with the period of
FCLK.
When SGFMCLKD is written, the DIVLD bit is set automatically. If DIVLD
is 0, SGFMCLKD has not been written since the last reset. Program and
erase commands will not execute if this register has not been written
(see
A command state machine is used to supervise the write sequencing of
program, erase, and verify commands. Before any command write
sequence is started, it is necessary to write the BKSEL field SGFMMCR
to select the banked set of registers associated with the FLASH physical
blocks to be programmed or erased (see
To prepare for a command, the CBEIF flag should be tested to ensure
that the address, data, and command buffers are empty. If CBEIF is set,
the command write sequence can be started.
Freescale Semiconductor, Inc.
Second Generation FLASH for M•CORE (SGFM)
For More Information On This Product,
10.8.3.4 FLASH User Mode Illegal
SYS
FCLK =
DIV[5:0] =
= 33 MHz, writing $54 to SGFMCLKD will set FCLK to
Go to: www.freescale.com
1 + (PRDIV8 x 7)
DIV[5:0] + 1
1 + (PRDIV8 x 7)
f
f
SYS
SYS
200 kHz
= 12.8 MHz, so PRDIV8 = 1
f
SYS
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
=
SYS
=
1 + (1 x 7)
33 MHz
20 + 1
= 33 MHz:
Figure 10-2
Operations).
1 + (1 x 7)
200 kHz
33 MHz
= 196.43 kHz
for more details).
= 20
MOTOROLA