MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 538
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface Module (EBI)
20.7.2.1 State 1 (X1)
20.7.2.2 Optional Wait States (X2W)
20.7.2.3 State 2 (X2)
Advance Information
538
The EBI drives the address bus. The TSIZ[1:0] pins are driven to indicate
the number of bytes in the transfer. TC[2:0] pins are driven to indicate
the type of access. CS may be asserted to drive a device. OE is negated.
Later in state 1, R/W is driven low indicating a write cycle. One or more
EB pins are asserted, depending on the size and position of the data to
be transferred.
If either the external TA pin or internal chip-select transfer acknowledge
signal is asserted before the end of state 1, the EBI proceeds to state 2.
Wait states are inserted until the slave asserts the TA pin or the internal
chip-select transfer acknowledge signal is asserted. The EBI drives its
data onto data bus lines D[31:16] and/or D[15:0] on the first optional wait
state. Wait states are counted in full clocks.
If the data was not already driven during optional wait states, the EBI
drives its data onto D[31:16] and/or D[15:0] in state 2.
EB is negated by the end of state 2. The address bus, data bus, R/W,
CS, TC[2:0], and TSIZ[1:0] pins remain valid through state 2 to allow for
static memory operation and signal skew.
Figure 20-3
and without wait states and show M•CORE bus activity.
Freescale Semiconductor, Inc.
For More Information On This Product,
External Bus Interface Module (EBI)
Go to: www.freescale.com
and
Figure 20-4
illustrate external bus master cycles with
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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