MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 160
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Power Management
6.4.4 JTAG
6.4.5 Interrupt Controller
6.4.6 Edge Port
6.4.7 Random-Access Memory (RAM)
Advance Information
160
The JTAG (Joint Test Action Group) controller logic is clocked using the
TCLK input and is not affected by the system clock. The JTAG cannot
generate an event to cause the CPU to exit any low-power mode.
Toggling TCLK during any low-power mode will increase the system
current consumption.
The interrupt controller is not affected by any of the low-power modes.
All logic between the input sources and generating the interrupt to the
M•CORE processor will be combinational to allow the ability to wakeup
the CPU processor during low-power stop mode when all system clocks
are stopped.
A fast interrupt request will cause the CPU to exit a low-power mode only
if the FE bit in the CPU’s PSR register is set. A normal interrupt request
will cause the CPU to exit a low-power mode only if the IE and EE bits in
the CPU’s PSR register are set.
In wait and doze modes, the edge port continues to operate normally and
may be configured to generate interrupts (either an edge transition or
low level on an external pin) to exit the low-power modes.
In stop mode, there are no clocks available to perform the edge detect
function. Thus, only the level detect logic is active (if configured) to allow
any low level on the external interrupt pin to generate an interrupt (if
enabled) to exit the stop mode.
The random-access memory (RAM) is disabled during any low-power
mode. No recovery time is required when exiting any low-power mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Power Management
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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