MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 440
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
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Queued Analog-to-Digital Converter (QADC)
19.8.4 Port QA and QB Data Direction Register (DDRQA and DDRQB)
Advance Information
440
NOTE:
The Port QA and QB Data Direction Register (DDRQA and DDRQB) are
associated with port QA and QB digital I/O pins. Setting a bit in these
registers configures the corresponding pin as an output. Clearing a bit in
these registers configures the corresponding pin as an input. During
QADC initialization, port QA and QB pins that will be used as direct or
multiplexed analog inputs must have their corresponding data direction
register bits cleared. When a port QA or QB pin that is programmed as
an output is selected for analog conversion, the voltage sampled is that
of the output digital driver as influenced by the load.
When the MUX (externally multiplexed) bit is set in QACR0, the data
direction register settings are ignored for the bits corresponding to
PQA[1:0], the two multiplexed address (MA[1:0]) output pins. The
MA[1:0] pins are forced to be digital outputs, regardless of their data
direction setting, and the multiplexed address outputs are driven. The
data returned during a port data register read is the value of the MA[1:0]
pins, regardless of their data direction setting.
Similarly, when the external trigger pins are assigned to port pins and
external trigger queue operating mode is selected, the data direction
setting for the corresponding pins, PQA3 and/or PQA4, is ignored. The
port pins are forced to be digital inputs for ETRIG1 and/or ETRIG2. The
data returned during a port data register read is the value of ETRIG[2:1]
pins, regardless of their data direction setting.
Use caution when mixing digital and analog inputs. They should be
isolated as much as possible. Rise and fall times should be as large as
possible to minimize ac coupling effects.
Freescale Semiconductor, Inc.
For More Information On This Product,
Queued Analog-to-Digital Converter (QADC)
Go to: www.freescale.com
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
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