MMC2114CFCAG33 Freescale Semiconductor, MMC2114CFCAG33 Datasheet - Page 253
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MMC2114CFCAG33
Manufacturer Part Number
MMC2114CFCAG33
Description
IC MCU 32BIT 33MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCorer
Specifications of MMC2114CFCAG33
Core Processor
M210
Core Size
32-Bit
Speed
33MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
MMC2114
Core
M-CORE
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
104
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
MCORE
No. Of I/o's
104
Ram Memory Size
32KB
Cpu Speed
33MHz
No. Of Timers
2
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MMC2114CFCAG33
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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11.7.2.2 Synthesizer Status Register
MMC2114 • MMC2113 • MMC2112 — Rev. 1.0
MOTOROLA
Address: 0x00c3_0002
Reset:
Read: PLLMODE PLLSEL
Write:
STPMD[1:0] — Stop Mode Bits
The Synthesizer Status Register (SYNSR) is a read-only register that
can be read at any time. Writing to the SYNSR has no effect and
terminates the cycle normally.
STPMD[1:0] control PLL and CLKOUT operation in stop mode as
shown in
Freescale Semiconductor, Inc.
Notes:
STPMD[1:0]
For More Information On This Product,
Note 1
1. Reset state determined during reset configuration.
2. See the LOCKS and LOCK bit descriptions.
Bit 7
Figure 11-3. Synthesizer Status Register (SYNSR)
00
01
10
11
Table 11-4. STPMD[1:0] Operation in Stop Mode
Table
Go to: www.freescale.com
= Writes have no effect and the access terminates without a transfer error exception.
Note 1
6
Clock Module
11-4.
Disabled
Disabled
Disabled
Disabled
System
Clocks
PLLREF
Note 1
5
Operation During Stop Mode
LOCKS
Note 2
Disabled
Disabled
Enabled
Enabled
4
PLL
Note 2
LOCK
3
Disabled
Enabled
Enabled
Enabled
OSC
Memory Map and Registers
LOCS
2
0
Advance Information
CLKOUT
Disabled
Disabled
Disabled
Enabled
1
0
0
Clock Module
Bit 0
0
0
253
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